Jakub Breier

Hardware Security Researcher & Architect

jakub.jpeg

I am a hardware security researcher with 10+ years of experience in fault injection, side-channel analysis, cryptography, and AI model security, spanning top academic venues (2,400+ citations, h-index 28) and safety-critical industry applications. My work bridges deep implementation-level security research with real-world deployment in automotive and embedded systems.

Currently, I lead the security strategy at TTControl GmbH in Vienna, where I oversee the end-to-end security lifecycle and ISO/SAE 21434 compliance for the company portfolio of automotive/off-highway Electronic Control Units (ECUs) and Human-Machine Interfaces (HMIs).

Core Impact & Expertise

  • Hardware Security Depth: Recognized expert in Fault Injection Attacks (FIA), Side-Channel Analysis (SCA), Symmetric Cryptography (Co-author of DEFAULT, Baksheesh), and Post-Quantum Cryptography (Co-author of ASCON-SIGN, a NIST PQC round 1 candidate). Author of Cryptography and Embedded Systems Security (Springer, 2024).
  • Global Regulatory Governance: Deep familiarity with EU Cyber Resilience Act (CRA) and Machinery Regulation compliance in safety-critical automotive contexts.
  • Safety-Security Integration: Designing certifiable security architectures that coexist with high-integrity functional safety (ISO 26262 / ASIL-D) requirements.

Professional Background

Before my current role, I served as a Senior Scientist at Silicon Austria Labs, Principal Research Fellow at HP-NTU Digital Manufacturing Corporate Lab, and held various research-related roles at Underwriters Laboratories (UL), and Temasek Laboratories in Singapore. This trajectory from high-end evaluation labs to industrial leadership allows me to manage security not just as a “checklist,” but as a resilient technical moat.

I hold a Ph.D. in Information Security and am a Certified Information Systems Security Professional (CISSP) and Certified Automotive Cybersecurity Professional (CACSP). My core belief: meaningful hardware security research must be rooted in understanding how attacks work at the silicon level – and how real systems fail.

news

Feb 1, 2026 I will serve as a co-chair of the Hardware and System Security track at The IEEE/ACM International Symposium on Low Power Electronics and Design ISLPED 2026.
Dec 10, 2025 I will serve on the Editorial Board of the IACR Communications in Cryptology 2026 CiC.
Nov 1, 2025 I will serve on the PC of the Hardware Security: Attack and Defense track at The Chips To Systems Conference DAC 2026.
Sep 1, 2025 I will serve on the PC of the IEEE International Symposium on Hardware Oriented Security and Trust HOST 2026.

selected publications

  1. CCS
    Practical Fault Attack on Deep Neural Networks
    Jakub Breier, Xiaolu Hou, Dirmanto Jap, Lei Ma, Shivam Bhasin, and Yang Liu
    In Proceedings of the 2018 ACM SIGSAC Conference on Computer and Communications Security, 2018
    arXiv
  2. TDSC
    FooBaR: Fault Fooling Backdoor Attack on Neural Network Training
    Jakub Breier, Xiaolu Hou, Martı́n Ochoa, and Jesus Solano
    IEEE Transactions on Dependable and Secure Computing, 2023
    arXiv Code
  3. Textbook
    Cryptography and Embedded Systems Security
    Xiaolu Hou, and Jakub Breier
    2024
    HTML PDF Supp
  4. TVLSI
    Make Shuffling Great Again: A Side-Channel Resistant Fisher-Yates Algorithm for Protecting Neural Networks
    Leonard Puškáč, Marek Benovič, Jakub Breier, and Xiaolu Hou
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2025
    arXiv
  5. ARES
    Side-Channel Analysis of OpenVINO-Based Neural Network Models
    Zdenko Lehockỳ, Jakub Breier, Dirmanto Jap, Shivam Bhasin, and Xiaolu Hou
    In International Conference on Availability, Reliability and Security, 2025
    arXiv